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september 2014 rev. 1.4a www.microsemi.com 1 ? 2014 microsemi corporation regulating pulse width modulator block diagram +v in ground sync r t c t discharge compensation inv. input n.i. input soft-sart shutdown 5k 5k error amp v in v ref 50 a latch s p.w.m. f/f oscillator osc output to internal circuitry reference regulator u.v. lockout v ref r q q + + v c output a output b output a output b sg1527a output stage sg1525a output stage v c figure 1 block diagram features ? 8v to 35v operation ? 5.1v reference trimmed to ? 1% ? 100hz to 500khz oscillator range ? separate oscillator sync terminal ? adjustable deadtime control ? internal soft-start ? input undervoltage lockout ? latching p.w.m. to prevent multiple pulses ? dual source/sink output d ri vers high reliability features following are the high reliability features of sg1525a and sg1527a: ? available to mil-std- 883 , ? 1.2.1 ? mil-m38510/12602bea - jan1525aj ? mil-m38510/12604bea - jan1527aj ? msc-ams level s processing available description the sg1525a/1527a series of pulse width modulator integrated circuits are designed to offer improved performance and lower external parts count when used to implement all types of switching power supplies. the on-chip +5.1 v reference is trimmed to 1% initial accuracy and the input common-mode range of the erro r amplifier includes the reference voltage, eliminating external potentiometers and divider resistors. a sync input to the oscillator allows multiple units to be slaved together, or a single unit t o be synchronized to an external system clock. a single resistor between the c t pin and the discharge pin provides a wide range of deadtime adjustment. these devices also feature built-in soft-start circuitry with only a timing capacitor required externally. a shutdow n pin controls both the soft-start circuitry and the output stages, providi ng instantaneous turn-off with soft-start recycle for slow tu rn-on. these functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor d ischarged for input voltages less than that required for normal operation. another unique feature of these pwm circuits is a latch following the comparator. once a pwm pulse has been terminated for an y reason, the outputs remain off for the duration of the pe riod. the latch is reset with each clock pulse. the output stages are totem- pole designs capable of sourcing or sinking in excess of 200ma. the sg1525a output stage features nor logic, giving a low output for an off state. the sg1527a utilizes or logic, which results in a high output level when off . sg1525a/sg2525a/sg3525a sg1527a/sg2527a/sg3527a downloaded from: http:///
regulating pulse width modulator 2 connection diagrams and ordering information ambient temperature type package part number packaging type connection diagram -55c to 125c j 16 -pin ceramic dip sg1525aj- 883 b cerdip 5 4 3 2 1 inv. input soft-start c sync n.i. input 6 15 14 13 12 11 16 7 8 9 10 discharge r output a ground v c v output b +v t t ref in shutdown compensation osc. output n package: rohs compliant / pb-free transition dc: 0503 n package: rohs / pb-free 100% matte tin lead finish SG1525AJ-JAN sg1525aj-desc sg1525aj sg1527aj- 883 b sg1527aj-jan sg1527aj-desc sg1527aj -25c to 85c sg2525aj sg2527aj -0c to 70 c sg3525aj sg3527aj -25c to 85c n 16 -pin plastic dip sg2525an pdip sg2527an -0c to 70 c sg3525an sg3527an -25c to 85c dw 16 - pin wide body plastic soic sg2525adw soic 5 4 3 2 1 inv. input shutdown compensation soft-start sync n.i. input 6 15 14 13 12 11 16 7 8 9 10 c t r t ground v c output b v ref +v in output a osc. output discharge dw package: rohs compliant / pb- free transition dc: 0516 dw package: rohs / pb-free 100% matte tin lead finish sg2527adw -0c to 70c sg3525adw sg3527adw -55c to 125c l 20 -pin ceramic leadless chip carrier (lcc) sg1525al-883b clcc 5 4 3 2 1 13. shutdown 10. soft-start 7. c 5. osc. output 4. sync 3. n.i. input 6 15 14 13 12 11 16 17 18 1920 78 9 10 15. ground 17. v c 18. output b 20. v ref 19. +v in 14. output a 2. inv. input 1. n.c. 16. n.c. 11. n.c. 12. comp 6. n.c. 9. discharge t 8. r t sg1525al sg1527al-883b sg1527al notes: 1. contact factory for jan and desc product availability. 2. all packages are viewed from the top. 3. hermetic packages j & l use sn63pb37 hot solder dip lead finish, con tact factory for availability of rohs complian t versions. downloaded from: http:///
absolute maximum ratings1 3 absolute maximum ratings 1 parameter value units supply voltage (+v in ) 40 v collector supply voltage (v c ) 40 v logic inputs -0.3 to 5.5 v analog inputs -0.3 to v in v output current, source or sink 5 00 ma reference load current 50 ma oscillator charging current 5 ma operating junction temperature hermetic (j, l packages) 150 c plastic (n, dw packages) 150 c storage temperature range -65 to 150 c lead temperature (soldering, 10 seconds) 300 c rohs peak package solder reflow temp. (40 s max. exp.) 260 (+0, - 5) c note: values beyond which damage may occur thermal data parameter value units j package thermal resistance-junction to case, jc 30 c/w thermal resistance-junction to ambient, ja 80 c/w n package thermal resistance-junction to case, jc 40 c/w thermal resistance-junction to ambient, ja 65 c/w dw package thermal resistance-junction to case, jc 40 c/w thermal resistance-junction to ambient, ja 95 c/w l package thermal resistance-junction to case, jc 35 c/w thermal resistance-junction to ambient, ja 120 c/w notes: 1. junction temperature calculation: t j = t a + (p d ja ). 2. the above numbers for jc are maximums for the limiting thermal resistance of the package in a sta ndard mounting configuration. the ja numbers are meant to be guidelines for the thermal performance of th e device/pc-board system. all of the above assume no ambient airflow. downloaded from: http:///
regulating pulse width modulator 4 recommended operating conditions 1 parameter value units input voltage (+v in ) 8 to 35 v collector voltage (v c ) 4.5 to 35 v sink/source load current (steady state) 0 to 100 ma sink/source load current (peak) 0 to 400 ma reference load current 0 to 20 ma oscillator frequency range 0.1 to 350 k hz oscillator timing resistor (r t ) 2 to 150 k ? deadtime resistor range (r d ) 0 to 500 ? maximum shutdown source impedance 5 k ? oscillator timing capacitor (c t ) 0.001 to 0.1 f operating ambient temperature range 1 sg1525a/sg1527a -55 to 125 c sg2525a/sg2527a -25 to 85 c sg3525a/sg3527a 0 to 70 c note: range over which the device is functional. electrical characteristics (unless otherwise specified, these specifications apply over the operating ambient temperatures for sg1525a/sg1527a with - 55 c t a 125 c, sg 2525a/sg2 527a with - 25 c t a 85 c, sg3525a/sg3527a with 0c t a 70c, and +v in = 20v. low duty cycle pulse testing techniques are used that maintains junction and case temperatures equal to t he ambient temperature.) parameter test conditions sg1525a/2525a sg1527a/2527a sg3525a sg3527a units min typ max min typ max reference section 1 output voltage t j = 25 ? c 5.05 5.10 5.15 5.00 5.10 5.20 v line regulation v in = 8v to 35v 10 30 10 30 mv load regulation i l = 0 to 20ma 20 50 20 50 mv temperature stability 1 over operating temperature range 20 50 20 50 mv total output voltage range 1 over line, load and temperature 5.00 5.20 4.95 5.25 v short circuit current v ref = 0v, t j = 25 ? c 80 100 80 100 ma output noise voltage 1 10hz f 10 khz, t j = 25c 40 200 40 200 ? vrms long term stability 1 t j = 1 25 ? c 20 50 20 50 mv/khr notes: 1. these parameters, although guaranteed over the recommended operatin g conditions, are not 100% tested in production. 2. f osc = 40 khz (r t = 3.6k ? , c t = 0.01f , r d = 0?. ). 3. applies to sg1525a/2525a/3525a only, due to polarity of output pulses. downloaded from: http:///
electrical characteristics (continued) 5 electrical characteristics ( continued ) parameter test conditions sg1525a/2525a sg1527a/2527a sg3525a/sg3527a units min typ max min typ max oscillator section 2 initial accuracy t j = 25 ? c 37.6 40 42.4 37.6 40 42.4 khz voltage stability v in = 8v to 35v 0.3 1 1 2 % temperature stability 1 min t j max 3 6 3 6 % minimum frequency 1 r t = 150k , c t = 0.1f 150 150 hz maximum frequency 1 r t = 2 k ? , c t = 1nf 350 350 khz current mirror i rt = 2ma 1.7 2.0 2.2 1.7 2.0 2.2 ma clock amplitude 3.0 3.5 3.0 3.5 v clock width t j = 25 ? c 0.3 0.5 1.0 0.3 0.5 1.0 s sync threshold 1.2 2.0 2.8 1.2 2.0 2.8 v sync input current sync voltage = 3.5v 1.0 2.5 1.0 2.5 ma error amplifier section (v cm = 5.1v) input offset voltage 0.5 5 2 10 mv input bias current 1 10 1 10 a input offset current 1 1 a dc open loop gain r l 10m , t j = 25 ? c 60 75 60 75 db output low level 0.2 0.5 0.2 0.5 v output high level 3.8 5.6 3.8 5.6 v common mode rejection v cm = 1.5v to 5.2 v 60 75 60 75 db supply voltage rejection v in = 8v to 35v 50 60 50 60 db pwm comparator section 2 minimum duty cycle v comp = 0.6v 0 0 % maximum duty cycle v comp = 3.6v 45 49 45 49 % input threshold 2 zero duty cycle 0.6 0.9 0.6 0.9 v maximum duty cycle 3.3 3.6 3.3 3.6 v input bias current 0.05 2.0 0.05 2.0 a soft-start section soft start current v shutdown = 0v 25 50 80 25 50 80 a soft start voltage v shutdown = 2v 0.4 0.6 0.4 0.6 v shutdown input current v shutdown = 2.5v 0.4 1.0 0.4 1.0 ma downloaded from: http:///
regulating pulse width modulator 6 parameter test conditions sg1525a/2525a sg1527a/2527a sg3525a/sg3527a units min typ max min typ max output drivers section (each transistor, v c = 20v) output high level i source = 20ma 18 19 18 19 v i source = 100ma 17 18 17 18 v output low level i sink = 20ma 0.2 0.4 0.2 0.4 v i sink = 100ma 1.0 2.2 1.0 2.2 v undervoltage lockout v comp and v ss = high 6 7 8 6 7 8 v collector leakage 3 v c = 35v 200 200 a rise time c l = 1nf, t j = 25c 100 600 100 600 ns fall time c l = 1nf, t j = 25c 50 300 50 300 ns shutdown delay 1 v sd = 3v, c s = 0, t j = 25c 0.2 0.5 0.2 0.5 s total standby current standby current v in = 35v 14 20 14 20 ma notes: 1. these parameters, although guaranteed over the recommended operatin g conditions, are not 100% tested in production. 2. f osc = 40 khz (r t = 3.6k ? , c t = 0.01f , r d = 0? ). 3. applies to sg1525a/2525a/3525a only, due to polarity of output pulses. downloaded from: http:///
oscillator section 7 oscillator section v ref gnd sync r t c t discharge 400 a q 1 q 3 q 5 q 8 q 6 q 9 q 10 q 11 q 12 q 13 q 2 q 4 q 7 16 6 53 7 12 7.4k 14k 2k 25k q 14 3k 250 4 clock blanking to output ramp to pwm 1k 23k 1k 5 pf 2k figure 2 oscillator schematic c t = 1 nf c t = 2 nf c t = 5 nf c t = .01 f c t = .02 f c t = . 05 f c t = 0. 1 f r d = 0 200 100 50 20 10 5 20 1 2 5 10 20 50 100 200 500 1000 2000 5000 r d c t 6 5 7 r t charge time - s timing resistor (r t ) - k ? figure 3 oscillator charge time versus r t and c t c t = 1 nf c t = 2 nf c t = 5 nf c t = . 01 f c t = . 02 f c t = . 05 f c t = 0. 1 f 500 400 300 200 100 0 0.2 0.5 1 10 20 50 100 200 25 discharge time - ms deadtime resistor (r d ) - ? figure 4 oscillator discharge time versus r d and c t downloaded from: http:///
regulating pulse width modulator 8 error amplifier section 5.8 v inv. input q 2 q 3 +v in q 4 q 1 1 2 15 9 to pwm comparator 100 a 200 a 30 ? n.i. input comp figure 5 error amplifier r z c p 1 2 80 60 40 20 0 10 r z = 0 r z = 20k c p = 0 c p = 1n f 1 10 100 1k 10k 100k 1m 10m + - frequency - hz voltage gain - db figure 6 error amplifier open-loop frequency response output section q1 q2 q3 q4 q5 q6 q7 q8 q9 q11 q6 omitted in sg1527a 5k 10k 10k +v ref +v in +v c 5k 2k 13 clock pwm f/f 1114 output q10 figure 7 output circuit (? circuit shown) 4 31 20 .01 .02 .03 .05 .10 .20 .30 .50 1a v in = 20 v t a = 25c source sat. v c - v oh sink sat. v ol figure 8 output saturation characteristics downloaded from: http:///
application information 9 application information +v supply +v c gnd 13 11 14 12 b a r 2 r 1 q1 to output filter return sg1525a for single-ended supplies, the driver outputs are grounded. the v c terminal is switched to ground by the totem-pole source transistors on alternate oscillator cycles. +v supply r 1 c 1 r 2 c 2 r 3 q 1 q 2 t 1 ab gnd sg1525a +v c 13 12 14 11 return in conventional push-pull bipolar designs, forward base drive is controlled by r 1 - r 3 .rapid turn-off times for the power devices are achieved with speed-up capacitors c 1 and c 2. a b gnd sg1525a +v c 13 12 14 11 r 1 q 1 q 2 return +v supply t 1 the low source impedance of the output drivers provides rapid charging of power fet input capacitance while minimizing external components. 1312 14 11 return +v supply q 1 q 2 r 1 r 2 t 1 a b gnd sg1525a +v c t 2 c 1 c 2 r 1 low power transformers can be driven directly by the sg1525a. automatic reset occurs during deadtime, when both ends of the primary winding are switched to ground. downloaded from: http:///
regulating pulse width modulator 10 shutdown options 1. use an external transistor or open-collector comparator to pul l down on the comp terminal. this sets the pwm latch turning off both outputs. if the shutdown signal is momentary, pulse- by -pulse protection can be accomplished as the pwm latch resets with each clock pulse . 2. the same results can be accomplished by pulling dow n on the soft-start terminal with the difference that on this pin, shutdown does not affect the amplifier compensation network but must dis charge any soft-start capacitor. 3. apply a positive-going signal to the shutdown terminal. thi s provides most rapid shutdown of the outputs but will not immediately set the pwm latch if there is a so ft-start capacitor. this capacitor discharges but with a current of approximately twice the charging current. 4. the shutdown terminal can be used to set the pwm latch on a pulse- by -pulse basis if there is no external capacitance on soft-start terminal. slow turn-on may still be accomplished by applying an external capacitor, blocking diode, and charging resistor to the com p terminal. (see sg1524 application note). v ref clock sync 3 k? 10 k? 1.5 k? pwm adj 0.009f 0.1f ramp 0.001f deadtime 3.6 k? 100 ? 10 k? 0.01f comp + _ e/a o s c i ll a t o r flip/ flop reference regulator 0.1f r t c t 1 = v os 2 = i(+) 3 = i(-) 1 3 2 2 31 2 2 3 3 v/i meter _ + d.u.t 50 a 5k 5 k a b 1 1 out a out b gnd softstart 5f shutdown 2k 2k v ref + 1k, 1w (2) 0.1f v c 0.1f +v in pwm 16 4 3 6 75 9 1 2 8 12 14 11 13 15 10 figure 9 sg1525a/1527a lab test fixture downloaded from: http:///
package outline dimensions 11 package outline dimensions controlling dimensions are in metric, inches equivalents are sh own for general information. h e a2 a1 c b l e d 1 8 9 16 seating plane a dim millimeters inches min max min max a 2. 06 2.65 0.081 0.104 a1 0.10 0.30 0.004 0.012 a2 2. 03 2.55 0.080 0.100 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 10 .08 10. 50 0.3 97 0.413 e 7. 40 7.60 0.291 0.299 e 1.27 bsc 0.05 bsc h 10.00 10.65 0.394 0.419 l 0.40 1.27 0.016 0.050 0 8 0 8 *lc - 0.10 - 0.004 *lead co planarity note: dimensions do not include protrusions; these shall not exceed 0.155mm (.006) on any side. lead dimension shall not include solder coverage. dimensions are in mm, inches are for reference only. figure 10 dw 16 -pin sowb package dimensions a e1 d e b l e c b1 s eating p lane 1 a2 a1 dim millimeters inches min max min max a - 5.33 - 0.210 a1 0.38 - 0.015 - a2 3.30 typ. 0.130 typ. b 0.36 0.56 0.014 0.022 b1 1.14 1.78 0.045 0.070 c 0.20 0.36 0.008 0.014 d 18.67 19.69 0.735 0.775 e 2.54 bsc 0.100 bsc e 7.62 8.26 0.300 0.325 e1 6.10 7.11 0.240 0.280 l 2.92 0.381 0.115 0.150 - 15 - 15 note: dimensions do not include protrusions; these shall not exceed 0.155mm (.006) on any side. lead dimension shall not include solder coverage. dimensions are in mm, inches are for reference only. figure 11 n 16-pin plastic dual inline package dimensions downloaded from: http:///
regulating pulse width modulator 12 package outline dimensions (continued) controlling dimensions are in inches, metric equivalents are show n for general information. d e 9 16 1 8 ea b h b2 c seating plane e a q l dim millimeters inches min max min max a - 5.08 - 0.200 b 0.38 0.51 0.015 0.020 b2 1.04 1.65 0.045 0.065 c 0.20 0.38 0.008 0.015 d 19.30 19.94 0.760 0.785 e 5.59 7.11 0.220 0.280 e 2.54 bsc 0.100 bsc ea 7.37 7.87 0.290 0.310 h 0.63 1.78 0.025 0.070 l 3.18 5.08 0.125 0.200 - 15 - 15 q 0.51 1.02 0.020 0.040 note: dimensions do not include protrusions; these shall not exceed 0.155mm (.006) on any side. lead dimension shall not include solder coverage. figure 12 j 16 -pin ceramic dual inline package dimensions d e3 l l2 b1 e b3 a2 a1 a 1 3 8 13 18 h e dim millimeters inches min max min max d/e 8.64 9.14 0.340 0.360 e3 - 8.128 - 0.320 e 1.270 bsc 0.050 bsc b1 0.635 typ 0.025 typ l 1.02 1.52 0.040 0.060 a 1.626 2.286 0.064 0.090 h 1.016 typ 0.040 typ a1 1.372 1.68 0.054 0.066 a2 - 1.168 - 0.046 l2 1.91 2.41 0.075 0.95 b3 0.203r 0.008r note: all exposed metalized area shall be gold plated 60 micro-inch minimum thickness over nickel plated unless otherwise specified in purchase order. figure 13 l 20 -pin ceramic lcc package outline dimensions downloaded from: http:///
sg1525a/sg1527a .1 /09.14 ? 2014 microsemi corporation. all rights reserved. microsemi and the micros emi logo are trademarks of microsemi corporation. all other trademarks and service marks are the pr operty of their respective owners. microsemi corporate headquarters one enterprise, aliso viejo ca 92656 usa within the usa: +1 (800) 713-4113 outside the usa: +1 (949) 380-6100 sales: +1 (949) 380-6136 fax: +1 (949) 215-4996 e-mail: sales.support@microsemi.com microsemi corporation (nasdaq: mscc) offers a comprehensive portfol io of semiconductor and system solutions for communications, defense and security, aerospace, and industrial markets. products include high-performance and radiation-hard ened analog mixed-signal integrated circuits, fpgas, socs, and asics; power management produc ts; timing and synchronization devices and precise time solutions, setti ng the world's standard for time; voice processing devices; rf solutions; discrete components; sec urity technologies and scalable anti-tamper products; power-over-ethernet ics and midspans; as well as custom design capabilities and services. microsemi is headquartered in aliso viejo, calif. and has approximately 3,400 employees globally. learn more at www.microsemi.com . downloaded from: http:///

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